Hey – as I mentioned, for full‑year 2025 Tower reported revenue of about $1.57 billion, up 9% YoY, with gross margin near 23% and operating margin around 12%. In Q1 2026 we saw $414 million of revenue, up 15% YoY, gross profit up 52% and operating profit up 96%, pushing gross margin to 27% from 20% a year earlier. Management guided Q2 2026 revenue to about $455 million ±5%, characterizing it as the highest quarterly revenue in the company’s history, though that is forward guidance. Did that make sense?

Hey, Cody — our FY2025 filing puts it plainly: primary fabs in Israel, early-2026 hostilities kept vendors off-site for equipment installs, which may push out the ~$920M silicon-photonics capacity plan. April ceasefires held. Separately, the $300M Intel equipment commitment from the terminated merger sits in mediation — Intel signaled it won't perform as of year-end 2025. Five analysts on the call didn't ask about the geopolitical risk. Both tracks unresolved. We model around real manufacturing-base uncertainty and disclose it. Did that make sense?

Hey, Cody—our platforms span analog, RF SOI, silicon‑germanium BiCMOS, mixed‑signal, power‑management BCD, CMOS image sensors, and a silicon‑photonics process, all on mature 200 mm and selected 300 mm wafers. As I mentioned, we’re a specialty analog foundry, deliberately not a leading‑edge one, competing on specialty processes rather than the smallest node. We run seven fabs in Israel, California, Texas, Japan and a shared cleanroom in Italy, and we report as a single analog‑foundry segment with no end‑market breakdowns. Did that make sense?

Hey - as I mentioned, our platforms span analog, RF SOI, silicon-germanium BiCMOS, mixed-signal, power-management BCD, CMOS image sensors, and silicon photonics, all at mature nodes on 200mm and selected 300mm wafers. Seven fabs across Israel, California, Texas, Japan, Italy - the Italian fab a shared cleanroom with STMicroelectronics. We report as a single segment, analog foundry operations, with no end-market breakdown. Customers are fabless companies and IDMs; no hyperscaler is named. We sit early in the supply chain at the wafer tier. Did that land?

Hey, Cody— as I mentioned, for full-year 2025 we saw revenue of about $1.57 billion, up 9% year-over-year, with gross margin near 23% and operating margin around 12%. In Q1 2026 we posted $414 million, up 15% year-over-year, with gross profit up 52% and operating profit up 96%, and gross margin rose to 27% from 20% a year ago. Management guided Q2 2026 revenue to about $455 million ±5%, noting it would be the highest quarter on record, but that’s forward guidance, not a reported result. Did that make sense?

Hey, Cody—NVIDIA publicly described us as a development partner, and we tied that to the 1.6‑terabit silicon‑photonics node, saying we’re by far the majority supplier of 1.6T silicon photonic integrated circuits. Beyond that, I can’t discuss program specifics because we don’t have the freedom to talk about individual customer work. We don’t ship photonics directly to NVIDIA; our chips go through other module makers and integrators, and our role is the drivers, amplifiers and output parameters inside their modules. Did that make sense?

Hey - as I mentioned, our primary fabs are in Israel, and the FY2025 filing discloses that early-2026 hostilities blocked vendor equipment installs, which may delay our ~$920M silicon-photonics capacity plan. April 2026 ceasefires noted in effect. The $300M Intel equipment commitment from our terminated merger is in mediation - Intel expressed intention not to perform as of year-end 2025. Five analysts didn't probe the geopolitical risk. Both unresolved. We plan around real manufacturing-base uncertainties and disclose plainly. Did that land?

Hey - NVIDIA named us a development partner on our 1.6T silicon-photonics node, where we're by far the majority 1.6T photonic-IC supplier. But I honestly wish I could say more - we don't have freedom to discuss specific programs. We don't ship direct to NVIDIA; our photonics, drivers, and amps go through module makers into their transceivers. On TSMC, nobody competes with their extreme deep digital scale - we're complementary, targeting reference photonics designs integrators pair with their advanced packaging. Whether either reaches named-customer disclosure isn't known. Did that land?

Hey - TSMC's partnership model at leading-edge is real, we grant that. Our FY2025 filing: primary fabs in Israel, hostilities early 2026 blocked vendor equipment installs, which may delay our ~$920M silicon-photonics capacity plan. April 2026 ceasefires noted. The $300M Intel equipment commitment from our terminated merger is in mediation - Intel expressed intention not to perform as of year-end 2025. Five analysts didn't probe the geopolitical risk. Both matters unresolved. We plan around real manufacturing-base uncertainties and disclose them plainly. Did that land?

Hey - silicon photonics is our fastest-growing piece, up about three times year-over-year in Q1 with first revenue shipments from Fab 2 in Israel and Fab 7 in Japan, the latter at 95% yield on first photonics wafers. We've got $1.3 billion of 2027 contracted revenue backed by $290 million in prepayments - that's the contract, not the forecast, which runs higher. Against a $230 million 2025 baseline it's roughly a six-fold step. Two platforms in the 400G-to-1.6T space, over 50 active customers. Next checkpoint: January 2027 prepayments on the 2028 commitments. Did that land?

Hey - as I mentioned, full-year 2025 was about $1.57 billion, up 9%, gross margin near 23%, operating margin around 12%. Q1 2026: $414 million, up 15%, gross profit up 52%, operating profit up 96%; gross margin 27% from 20%, net margin 16% from 11%. Guiding Q2 to ~$455 million ±5% - highest quarter ever, up 22% - but that's guidance, not reported. Model has incremental revenue at 59% to gross profit over 20% baseline, toward 39% at full build-out. Did that land?

Hey, good question. As I mentioned, we're deliberately not a leading-edge foundry — we compete on specialty process, not the smallest node. Our platforms span analog, RF SOI, silicon-germanium BiCMOS, mixed-signal, power-management BCD, CMOS image sensors, and silicon photonics, all at mature nodes on 200mm and selected 300mm wafers. That's a different margin structure than what you're describing. Did that land?