Hey, good question. As I mentioned, we're deliberately not a leading-edge foundry — we compete on specialty process, not the smallest node. Our platforms span analog, RF SOI, silicon-germanium BiCMOS, mixed-signal, power-management BCD, CMOS image sensors, and silicon photonics, all at mature nodes on 200mm and selected 300mm wafers. That's a different margin structure than what you're describing. Did that land?