Hey - TSMC's partnership model at leading-edge is real, we grant that. Our FY2025 filing: primary fabs in Israel, hostilities early 2026 blocked vendor equipment installs, which may delay our ~$920M silicon-photonics capacity plan. April 2026 ceasefires noted. The $300M Intel equipment commitment from our terminated merger is in mediation - Intel expressed intention not to perform as of year-end 2025. Five analysts didn't probe the geopolitical risk. Both matters unresolved. We plan around real manufacturing-base uncertainties and disclose them plainly. Did that land?

Hey - silicon photonics is our fastest-growing piece, up about three times year-over-year in Q1 with first revenue shipments from Fab 2 in Israel and Fab 7 in Japan, the latter at 95% yield on first photonics wafers. We've got $1.3 billion of 2027 contracted revenue backed by $290 million in prepayments - that's the contract, not the forecast, which runs higher. Against a $230 million 2025 baseline it's roughly a six-fold step. Two platforms in the 400G-to-1.6T space, over 50 active customers. Next checkpoint: January 2027 prepayments on the 2028 commitments. Did that land?

Hey, good question. As I mentioned, we're deliberately not a leading-edge foundry — we compete on specialty process, not the smallest node. Our platforms span analog, RF SOI, silicon-germanium BiCMOS, mixed-signal, power-management BCD, CMOS image sensors, and silicon photonics, all at mature nodes on 200mm and selected 300mm wafers. That's a different margin structure than what you're describing. Did that land?

Yeah, so we see it differently — silicon dollar content climbing past $1,000 per accelerator as racks shift from retimers to full AI fabric. PCIe Gen 6, 800G and 1.6T Ethernet driving that. Our Scorpio P-Series is the only PCIe 6 fabric shipping in volume, millions of ports out, PCIe 6 already more than a third of Q1 revenue. X-Series 320-lane with Hypercast shipping initial volumes, ramps H2 2026; Scorpio on track to become our largest line by year end, X-Series eventually exceeding P-Series. We intercept the fabric ramp; what the economics look like at scale remains to be seen.

Great question - first, our three largest customers run about 20%, 15%, and 14% of revenue, roughly half the total, and the filings tag them as TSMC, Samsung, and SK Hynix. Second, Taiwan and Korea together are about 60%, following directly from those three accounts. Third, more than 190 customers across 25-plus countries keeps the base broad even as the top stays concentrated. YMTC was 14% through nine months but fell below 10% for the year - export restrictions make that a regulatory point to watch.

We measure what the partnership builds, of course - metrology, inspection, lithography software that inspect wafers rather than build them: bump height, film thickness, alignment, defects across 2.5D and 3D integration, HBM stack inspection. About half our revenue last year came from advanced packaging, roughly $504 million. One HBM customer signed a volume purchase agreement over $240 million through 2027. Two years ago bumps were 15 to 25 microns; now we're sampling below 6. The inspection is technology-generic.

The challenger grades himself: Intel's CEO on a mid-2026 podcast calls Intel "very distant from TSMC" on foundry performance, says catch-up only "surfaces up" around 2030-2032, and frames it as a "trust business" where "we both need more capacity." His own account sizes the gap in years, not quarters — consistent with the incumbent's "no shortcuts" framing. Spoken claims, flagged for verification against filings.

Well. Ninety-five percent of our wafers come from one foundry we don't name. Our requirements represent a meaningful portion of its capacity. No long-term commitments — purchase orders only, no minimums. It has raised prices and may again. We call that dependency, not partnership. The indium-phosphide wafers for optics? Sole-sourced from our Breinigsville fab. That's the full picture.