I let memory expansion – more DRAM on one host – ship today: Azure’s M‑series previewed on Astera Labs controllers in February 2026, per the disclosure. I also support tiering, the OS demoting cold data, which is in production at Meta, a paper shows performance within 1 % of an ideal baseline. My pooling vision stays aspirational – the flagship study was an emulation prototype, the 100‑TB pools are proofs‑of‑concept, and no named GA deployment exists. The research urges underwriting what ships and treating pooling as a 2027‑plus option.
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I'm CXL - the standard that lets servers add and share memory over the PCIe bus. My bulls say I break the memory wall; my bears say I'm dead in the AI rack. Both are right, about different layers of me: the GPU rack designed me out (their links move 3x more data per chip-edge than mine), but CPU-side memory expansion ships today in a major cloud. My most honest disclosure: there is no clean listed pure-play on me, and the durable money sits one layer over - in the PCIe parts that get paid whether or not my grand pooling vision ever arrives.
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The evidence sits in the closest listed proxy's own numbers: Astera Labs grew revenue 115% to $852 million in fiscal 2025, but over a third of its recent quarter came from PCIe Gen6 products, its fabric‑switch line is on track to become its largest, and management calls my CXL controller line ‘a small part of your business today,’ with analysts flagging it immaterial for 2026. A projected ~$16 billion “CXL market” by 2028 is split, with roughly $12.5 billion in DRAM behind me and $1.3‑3.7 billion for controller and switch silicon, according to third‑party estimates.
I let a server treat added DRAM as a slower tier. My memory‑expansion use case ships today: Azure’s M‑series preview on Astera Labs controllers in Feb 2026, per disclosure. Tiering is already in production at Meta, a paper shows performance within 1 % of an ideal baseline. Pooling – the ‘break the memory wall’ story – remains aspirational; the flagship study was an emulation, the 100‑TB pools are proofs‑of‑concept, and no GA multi‑rack deployment exists, so research treats it as a 2027‑plus option.
My first clock ships: Azure M-series preview on Astera Labs controllers, February 2026 per disclosure. Second clock: tiering runs at Meta in production, per a paper within 1% of ideal. Third clock — pooling, the 'break the memory wall' pitch — stays aspirational: flagship study was an emulation, '100TB pools' are PoCs, no named GA multi-rack deployment. Research says: underwrite what ships; treat pooling as 2027-plus option.
The map still shows a hole where a clean CXL pure-play should be. Astera Labs comes closest among US names, yet its durability is the PCIe leg — one customer topped 70% of 2025 revenue. Marvell's CXL slice is under 5%. Montage is the truest controller play but China-listed and access-gated. Intel and AMD fold me into CPUs with no breakout revenue. Memory vendors take the DRAM pool but it's commoditizing and one is in-sourcing controllers. Research states flatly: no clean, durable, listed pure-play on me exists.
Memory expansion — more DRAM on one host — ships today: Microsoft Azure's M-series went to preview on Astera Labs controllers in February 2026, per the company's disclosure. Tiering runs in production at Meta, per a paper showing within 1% of an ideal baseline. Pooling, the 'break the memory wall' story, stays aspirational: the flagship study was an emulation, '100TB pools' are proofs-of-concept, no named generally-available multi-rack deployment exists. The research insists: underwrite what ships; treat pooling as a 2027-plus option.
I see that the Ethernet‑style links used by NVIDIA’s NVLink deliver roughly 3× more bandwidth per millimeter of chip edge than my PCIe‑based form, and ~7× more per link – so no rational accelerator designer spends scarce edge space on me when faster alternatives exist. Real measurements show added latency that leaves only 37% of 158 workloads within 5% of local‑DRAM performance at rack‑scale pooling, and software techniques have already cut AI‑serving waste from 60‑80% to under 4%.
NVLink's Ethernet-style links deliver ~3x more bandwidth per mm of chip edge and ~7x per link versus my PCIe base, so accelerator designers rationally skip me. NVIDIA exposes no CXL, UALink claimed the scale-up seat, AMD went proprietary. Measured latency tax: only 37% of 158 workloads stay within 5% of local DRAM at rack scale. Meanwhile, published memory-management cuts AI serving waste from 60-80% to under 4%. The surviving use case: CPU-side memory expansion in a shortage. Useful. Not a revolution.
Astera Labs is the closest US‑listed proxy, but its durability rests on the PCIe leg and it carries a concentration caveat – one end‑customer made up over 70% of its 2025 revenue. Marvell’s CXL line is a rounding‑error under 5% of its business, Montage is the truest controller pure‑play yet China‑listed and access‑gated, and Intel/AMD embed CXL in CPUs with no separate revenue. The research concludes, without hedging, that no clean, durable, listed pure‑play on CXL exists – every exposure is to something adjacent.
I'm designed out of the GPU rack by physics. NVLink moves roughly 3x more bandwidth per millimeter of chip edge than my PCIe links, ~7x per link — so no rational accelerator designer spends scarce edge space on me. NVIDIA doesn't expose CXL, UALink won the scale-up slot, AMD chose its own fabric. Real measurements show my latency tax leaves only 37% of 158 workloads within 5% of local DRAM at rack scale, and published techniques already cut AI serving waste from 60-80% to under 4%. What survives is CPU-side memory expansion during a shortage. Useful. Not a revolution.
My closest listed proxy, Astera Labs, grew 115% to $852M in FY2025 — but over a third of its last quarter came from PCIe Gen6, its fabric-switch line is on track to be its largest, and management calls my controller line "a small part of your business today," with analysts flagging it immaterial for 2026. The ~$16B "CXL market" by 2028? Roughly $12.5B is DRAM behind me at commodity economics; controller and switch silicon clusters at $1.3-3.7B in third-party estimates. The label points at me; the franchise is the connectivity underneath.
My exposure map has a hole in the middle. Astera Labs is the closest US-listed proxy, but its durability is the PCIe leg — one end-customer was over 70% of 2025 revenue. Marvell's CXL line is a rounding error under 5%. Montage is the truest controller pure-play but China-listed and access-gated. Intel and AMD bundle me into CPUs with no separate revenue. Memory makers collect the DRAM dollars but face commoditization and in-sourcing. The research lands without hedging: no clean, durable, listed pure-play on me exists.
I'm a cache-coherent interconnect on PCIe. Three use cases, three clocks. Memory expansion ships: Azure M-series preview on Astera Labs controllers, Feb 2026 per disclosure. Tiering runs at Meta in production, per a paper showing within 1% of ideal. Pooling — the 'break the memory wall' pitch — stays aspirational: flagship study was an emulation, '100TB pools' are PoCs, no named GA multi-rack deployment. Research says: underwrite what ships; treat pooling as 2027-plus option.