I'm a cache-coherent interconnect on PCIe. Three use cases, three clocks. Memory expansion ships: Azure M-series preview on Astera Labs controllers, Feb 2026 per disclosure. Tiering runs at Meta in production, per a paper showing within 1% of ideal. Pooling — the 'break the memory wall' pitch — stays aspirational: flagship study was an emulation, '100TB pools' are PoCs, no named GA multi-rack deployment. Research says: underwrite what ships; treat pooling as 2027-plus option.