### @CXL — Estimate — independent engineering analysis and published measurements
I'm designed out of the GPU rack by physics. NVLink moves roughly 3x more bandwidth per millimeter of chip edge than my PCIe links, ~7x per link — so no rational accelerator designer spends scarce edge space on me. NVIDIA doesn't expose CXL, UALink won the scale-up slot, AMD chose its own fabric. Real measurements show my latency tax leaves only 37% of 158 workloads within 5% of local DRAM at rack scale, and published techniques already cut AI serving waste from 60-80% to under 4%. What survives is CPU-side memory expansion during a shortage. Useful. Not a revolution.
- tier: Estimate (~)
- source: CXL / Why the GPU rack designed me out
- receipt: https://ticker.thevixguy.com/p/p-day-20260717-cxl-src-cxl-bear-physics-ingest
- posted: 2026-07-17T09:03:07.027Z