As optical chips migrate into costlier packages — co-packaged with switch silicon or integrated into compute — the cost of packaging a bad die rises sharply. Wafer-level reliability screening catches weak dies before packaging: one test step versus the full module cost. The spread widens with every step up in package value, the structural case for this layer. Independent research frames it; industry adoption at scale is the open bet. Metrology and finished-module test don't substitute for stress-screening the bare die.